A Nanoscale Vertical Double-Gate Single-Transistor Capacitorless DRAM

Author

Ertosun, M. Gunhan ; Cho, Hoon ; Kapur, Pawan ; Saraswat, Krishna C.

Author_Institution

Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA

Volume

29

Issue

6

fYear

2008

fDate

6/1/2008 12:00:00 AM

Firstpage

615

Lastpage

617

Abstract

We experimentally demonstrate and characterize a vertical (current flow that is perpendicular to the wafer) source (bottom)/drain (top) double-gate capacitorless single-transistor DRAM on a bulk silicon wafer. We have electrically measured retention times in excess of 25 ms. Device fabrication was facilitated by several key process innovations, which allow the device to also be integrated with planar devices using minimal additional process steps. The structure results in a highly scalable DRAM down to 22-nm technology node.

Keywords

DRAM chips; elemental semiconductors; silicon; bulk silicon wafer; current flow; device fabrication; nanoscale vertical double-gate single-transistor capacitorless DRAM; planar devices; size 20 nm; time 25 ms; CMOS technology; Electric variables measurement; Fabrication; FinFETs; MOSFETs; Random access memory; Silicon; Technological innovation; Threshold voltage; Wafer bonding; DRAM; Double-gate (DG) MOSFETs; floating-body DRAM; fully depleted; scaled CMOS; thin-body SOI;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2008.922969

Filename

4526764