A parasitic-insensitive area-efficient approach to realizing very large time constants in switched-capacitor circuits

Author

Nagaraj, K.

Author_Institution

AT&T Bell Labs., Murray Hill, NJ, USA

Volume

36

Issue

9

fYear

1989

fDate

9/1/1989 12:00:00 AM

Firstpage

1210

Lastpage

1216

Abstract

A novel switched-capacitor technique for realizing very large time constants is presented. The technique is insensitive to parasitic capacitances and is very area-efficient. It does not require a complicated clocking scheme. The technique yields a complete family of integrators which in turn can be used to realize higher-order filtering functions based on cascaded biquadratic sections or ladder filters. These integrators have been used to implement an experimental 60-Hz notch filter working from a 128-kHz clock

Keywords

active filters; integrating circuits; ladder networks; monolithic integrated circuits; notch filters; switched capacitor networks; 60 Hz; SC circuits; active filters; area-efficient; cascaded biquadratic sections; higher-order filtering functions; integrators; ladder filters; large time constants; lossless inverting integrator; notch filter; parasitic capacitances; parasitic-insensitive; switched-capacitor circuits; Clocks; Filtering; Filters; Frequency; Helium; Parasitic capacitance; Poles and zeros; Sampling methods; Switched capacitor circuits; Switching circuits;

fLanguage

English

Journal_Title

Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0098-4094

Type

jour

DOI

10.1109/31.34666

Filename

34666