• DocumentCode
    122724
  • Title

    WCET-aware dynamic code management on scratchpads for Software-Managed Multicores

  • Author

    Yooseong Kim ; Broman, David ; Jian Cai ; Shrivastaval, Aviral

  • Author_Institution
    Univ. of California, Berkeley, Berkeley, CA, USA
  • fYear
    2014
  • fDate
    15-17 April 2014
  • Firstpage
    179
  • Lastpage
    188
  • Abstract
    Software Managed Multicore (SMM) architectures have advantageous scalability, power efficiency, and predictability characteristics, making SMM particularly promising for real-time systems. In SMM architectures, each core can only access its scratchpad memory (SPM); any access to main memory is done explicitly by DMA instructions. As a consequence, dynamic code management techniques are essential for loading program code from the main memory to SPM. Current state-of-the-art dynamic code management techniques for SMM architectures are, however, optimized for average-case execution time, not worst-case execution time (WCET), which is vital for hard real-time systems. In this paper, we present two novel WCET-aware dynamic SPM code management techniques for SMM architectures. The first technique is optimal and based on integer linear programming (ILP), whereas the second technique is a heuristic that is suboptimal, but scalable. Experimental results with benchmarks from Mälardalen WCET suite and MiBench suite show that our ILP solution can reduce the WCET estimates up to 80% compared to previous techniques. Furthermore, our heuristic can, for most benchmarks, find the same optimal mappings within one second on a 2GHz dual core machine.
  • Keywords
    integer programming; linear programming; multiprocessing systems; real-time systems; DMA instructions; ILP; Malardalen WCET suite; MiBench suite; SMM architectures; WCET-aware dynamic SPM code management techniques; WCET-aware dynamic code management; advantageous scalability; average-case execution time; dual core machine; dynamic code management techniques; hard real-time systems; integer linear programming; power efficiency; predictability characteristics; scratchpad memory; scratchpads; software-managed multicores; worst-case execution time; Interference; Loading; Multicore processing; Real-time systems; Timing; Upper bound;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014 IEEE 20th
  • Conference_Location
    Berlin
  • ISSN
    1080-1812
  • Print_ISBN
    978-1-4799-4691-4
  • Type

    conf

  • DOI
    10.1109/RTAS.2014.6926001
  • Filename
    6926001