• DocumentCode
    122730
  • Title

    Overhead-aware temporal partitioning on multicore processors

  • Author

    Pathan, Risat Mahmud ; Stenstrom, Per ; Green, Lars-Goran ; Hult, Torbjorn ; Sandin, Patrik

  • Author_Institution
    Chalmers Univ. of Technol., Gothenburg, Sweden
  • fYear
    2014
  • fDate
    15-17 April 2014
  • Firstpage
    251
  • Lastpage
    262
  • Abstract
    Many previously proposed interface models for composability analysis of hierarchical scheduling are overhead-unaware, which is unsafe for real systems. This paper proposes an overhead-aware schedulability analysis to guarantee temporal partitioning among real-time applications/components hosted on a multicore platform. First, a new interface model and the method to generate an interface for a given component is proposed. Each interface has a tunable parameter d (degree) that can balance between abstraction and accuracy in capturing each component´s task-level timing constraints. Second, the problem of constructing an overhead-aware system-level schedule of all the components is addressed. The system designer has the flexibility to select parameters (e.g., allocated processor bandwidth) for each component such that overhead (e.g., preemptions across partitions) is minimized. Third, a slack distribution algorithm to reduce various overhead is proposed and its effectiveness is evaluated using randomly generated interface sets and also using workload of a real space-borne application provided by RUAG Space Sweden AB.
  • Keywords
    aerospace computing; microprocessor chips; multiprocessing systems; processor scheduling; RUAG Space Sweden AB; composability analysis; hierarchical scheduling; interface models; multicore platform; multicore processors; overhead-aware schedulability analysis; overhead-aware system-level schedule; overhead-aware temporal partitioning; randomly generated interface sets; real systems; slack distribution algorithm; space-borne application; task-level timing constraints; tunable parameter; Lead; Multicore processing; Processor scheduling; Program processors; Schedules; Servers; Upper bound;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Real-Time and Embedded Technology and Applications Symposium (RTAS), 2014 IEEE 20th
  • Conference_Location
    Berlin
  • ISSN
    1080-1812
  • Print_ISBN
    978-1-4799-4691-4
  • Type

    conf

  • DOI
    10.1109/RTAS.2014.6926007
  • Filename
    6926007