DocumentCode :
1227776
Title :
Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs
Author :
Chow, Eugene M. ; Fork, David K. ; Chua, Christopher L. ; Van Schuylenbergh, K. ; Hantschel, Thomas
Author_Institution :
Palo Alto Res. Center, Palo Alto, CA
Volume :
32
Issue :
2
fYear :
2009
fDate :
5/1/2009 12:00:00 AM
Firstpage :
372
Lastpage :
378
Abstract :
Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm times 6.5 mm with 48 spring contacts on a 0.8 mm times 0.65 mm grid array, each spring measuring 400 mum times 100 mum. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone >20 000 hot plate thermal cycles and >1000 oven thermal cycles without failure.
Keywords :
integrated circuit interconnections; integrated circuit testing; printed circuits; solders; thin films; wafer level packaging; eutectic solder; integrated circuit test; lead-free solder; organic printed circuit board; pick machine; place machine; screen printed solder paste; soldered flip chip interconnects; soldered stress-engineered microsprings; surface mount compatible process; thin film metallization; wafer-level packaging; Cantilever; compliant interconnects; fine pitch; flip chip; memory packaging; micro-spring; probing; stress-engineered; surface mount technology; wafer level packaging;
fLanguage :
English
Journal_Title :
Advanced Packaging, IEEE Transactions on
Publisher :
ieee
ISSN :
1521-3323
Type :
jour
DOI :
10.1109/TADVP.2008.2010507
Filename :
4811946
Link To Document :
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