Low hardware overhead implementation of 3-weight pattern generation technique for VLSI testing

Author

Gracia Nirmala Rani, D. ; Mangala Meenakshi, M.G. ; Marina, S. Amalin

fYear

2014

fDate

6-8 March 2014

Firstpage

1

Lastpage

5

Abstract

Pseudorandom Built-In Self-Test (BIST) generators have been most frequently used to test the integrated circuits and systems. This scheme requires more test patterns and consumes more testing time hence weighted pseudorandom BIST schemes have been proposed. These methodologies are used to drive down the number of test vectors. Most of the current VLSI chips have accumulators; hence they can be utilized efficiently to reduce the hardware of BIST pattern generation. Therefore in this paper a low hardware overhead implementation of 3-weight pattern generation technique is proposed to achieve high fault coverage and reduced testing time. The proposed scheme generates set of patterns for ISCAS c17 benchmark circuits with weights 0, 0.5, and 1.

Keywords

VLSI; automatic test pattern generation; built-in self test; 3-weight pattern generation technique; ISCAS c17 benchmark circuits; VLSI testing; built-in self-test; fault coverage; integrated circuit testing; low hardware overhead; pseudorandom BIST generators; test vectors; weighted pseudorandom BIST schemes; Adders; Benchmark testing; Built-in self-test; Circuit faults; Hardware; Vectors; Very large scale integration; Built-In Self-Test (BIST); VLSI testing; Weighted test pattern generation;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems (ICDCS), 2014 2nd International Conference on

Conference_Location

Combiatore

Type

conf

DOI

10.1109/ICDCSyst.2014.6926180

Filename

6926180