Residue arithmetic´s using reversible logic gates

The Residue number system (RNS) has been employed for efficient parallel carry-free arithmetic computations in DSP applications. Residue addition is the instrumental component in implementing residue converters and channels in RNS. On the other side Reversible Logic is becoming one of the potential power optimization techniques in Low Power CMOS design. In this research paper we have proposed CMOS implementation of two different reversible logic architectures for 4-bit generic modulo-m ripple residue adder using 4×4 TSG, DPG and 3×3 Fredkin Reversible logic gates and one architecture for 4-bit generic modulo-m carry look ahead residue adder using 4×4 RMF and 3×3 Fredkin Reversible logic gates along with two irreversible logic based 4-bit generic modulo-m residue adder one for irreversible 4-bit generic modulo-m ripple residue adder and another for 4-bit generic modulo-m carry look ahead adder. Proposed architectures are analyzed in terms of power, delay, garbage o/p, constant inputs and transistor count using 180nm technology node at 1.8 v with operating frequency of 200 MHz. It is observed that DPG based Reversible Residue Ripple adder has 40% more efficient than irreversible Residue Ripple adder and RMF based Reversible Residue CLA adder has 33% more efficient than irreversible Residue CLA added. The implementation is based on Reversible pass transistor Logic (R-CPL).