Title :
A new reasoning scheme for efficient redundancy addition and removal
Author :
Chang, Chih-Wei Jim ; Hsiao, Ming-Fu ; Marek-Sadowska, Malgorzata
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of California, Santa Barbara, CA, USA
fDate :
7/1/2003 12:00:00 AM
Abstract :
Redundancy addition and removal is a rewiring technique which, for a given target wire wt, finds a redundant alternative wire wa. The addition of wa makes wt redundant and, hence, removable without changing the overall circuit functionality. Incremental logic restructuring based on this technique has been used in many applications. However, in the earlier methods, the search for valid alternative wires required trial-and-error redundancy testing of a potentially large set of candidate wires. Here, we study the fundamental theory behind this technique and propose a new reasoning scheme (RAMFIRE), which directly identifies alternative wires without performing trial-and-error tests. Experimental results show speedup of up to 15 times than that of the best techniques in the literature.
Keywords :
circuit optimisation; combinational circuits; directed graphs; logic design; logic testing; network topology; redundancy; timing; Boolean network; RAMFIRE; alternative wire identification; combinational logic restructuring; directed acyclic graph; incremental logic restructuring; physical synthesis; reasoning scheme; redundancy addition; redundancy removal; redundant alternative wire; rewiring technique; target wire; timing optimization; Circuit synthesis; Circuit testing; Engines; Field programmable gate arrays; Logic; Minimization; Performance evaluation; Routing; Timing; Wires;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
DOI :
10.1109/TCAD.2003.814239