A 1.8-V 6-bit 1.3-GHz flash ADC in 0.25-μm CMOS

Author

Uyttenhove, Koen ; Steyaert, Michiel S J

Author_Institution

Picanol Ieper, Belgium

Volume

38

Issue

7

fYear

2003

fDate

7/1/2003 12:00:00 AM

Firstpage

1115

Lastpage

1122

Abstract

The design and optimization of a high-speed low-voltage CMOS flash analog-to-digital converter (ADC) are presented. The optimization procedures used during the design give the needed specifications of the different building blocks. Also, an extensive description of the implemented digital error correction technique is described. The used analog power supply is only 1.8 V. The maximum sampling speed is 1.3 GHz. The signal-to-noise-plus-distortion ratio (SNDR) at 133 kHz is 33.2 dB, and the SNDR at 500 MHz is 32 dB. The total power consumption of the converter at full speed is 600 mW and the total active area is only 0.13 mm². The ADC is implemented in a 0.25-μm pure digital CMOS technology.

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit optimisation; comparators (circuits); error correction; high-speed integrated circuits; low-power electronics; 0.25 micron; 1.3 GHz; 1.8 V; 6 bit; 600 mW; CMOS; digital error correction technique; flash ADC; high-speed converter; low-voltage converter; optimization procedures; sampling speed; signal-to-noise-plus-distortion ratio; total active area; total power consumption; Analog-digital conversion; CMOS technology; Design optimization; Energy consumption; Error correction; Low voltage; Power supplies; Sampling methods; Signal design; Signal resolution;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2003.813244

Filename

1208459