Electrical Characterization of Ordered Si:P Dopant Arrays

We report on the ability to fabricate arrays of planar, nanoscale, highly doped phosphorus dots in silicon separated by source and drain electrodes using scanning tunneling microscope lithography. We correlate ex situ electrical measurements with scanning tunneling microscope (STM) images of these devices and show that ohmic conduction can be achieved through the disordered array with a P coverage of 0.8times10¹⁴ cm^-2. In comparison, we show that an ordered array of P dots ~6 nm in diameter and containing ~50 P atoms separated by ~4 nm shows nonlinear I-V, characteristic of a series of metallic dots separated by tunnel barriers. These results highlight the use of STM lithography to pattern ordered dopants in silicon down to the sub-10 nm scale