Title :
Low voltage CMOS four-quadrant multiplier
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
fDate :
12/8/1994 12:00:00 AM
Abstract :
A new low voltage CMOS four-quadrant multiplier is presented. Simulation results show that, for a power supply of ±1.5 V the differential linear range is over ±0.8 V with the linearity error less than 2%. The total harmonic distortion is less than 1% with the input range up to ±0.6 V. The simulated -3 dB bandwidth of this multiplier is about 12 MHz. The proposed circuit is expected to be useful in low-voltage analogue signal processing applications
Keywords :
CMOS analogue integrated circuits; analogue multipliers; harmonic distortion; -1.5 to 1.5 V; 12 MHz; CMOS IC; LV analogue signal processing applications; THD; differential linear range; four-quadrant multiplier; linearity error; low voltage multiplier; total harmonic distortion;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19941427
