T-Rex, a blade packaging architecture for mainframe servers

Author

Katopis, George A. ; Becker, Wiren Dale ; Harrer, Hubert H.

Author_Institution

IBM Corp., Poughkeepsie, NY

Volume

28

Issue

1

fYear

2005

Firstpage

24

Lastpage

31

Abstract

In this paper, we describe the application of the blade packaging concept to the IBM zSeries eServer z990, code-named T-Rex. The advantages of such packaging architecture are highlighted and the challenges for the system performance are identified. The physical and electrical attributes of the five types of buses required to support a processing operating frequency of 1.25 GHz in a symmetric multiprocessing (SMP) architecture with up to 64 processor cores are tabulated. The evolution of the I/O circuits for each of these buses is described along with the bus cycle time and bandwidth trends

Keywords

computer architecture; file servers; mainframes; multichip modules; multiprocessing systems; system buses; 1.25 GHz; I-O circuits; IBM zSeries eServer z990; T-Rex; bandwidth trends; blade packaging architecture; blade packaging concept; blade servers; bus cycle time; computer architecture; computer system design; design methodology; electronic packaging; high-frequency digital signals; mainframe computers; mainframe servers; multichip modules; processor cores; semiconductor device packaging; symmetric multiprocessing architecture; Blades; Ceramics; Computer architecture; Connectors; Cooling; Electronics packaging; Glass; Integrated circuit interconnections; Multichip modules; Semiconductor device packaging; Blade servers; computer architecture; computer system design; design methodology; electronic packaging; high-frequency digital signals; mainframe computers; multichip modules (MCMs); semiconductor device packaging;

fLanguage

English

Journal_Title

Advanced Packaging, IEEE Transactions on

Publisher

ieee

ISSN

1521-3323

Type

jour

DOI

10.1109/TADVP.2004.841649

Filename

1391064