A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM

Author

Lu, Zhichao ; Fossum, Jerry G. ; Zhang, Weimin ; Trivedi, Vishal P. ; Mathew, Leo ; Sadd, Michael

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Florida, Gainesville, FL

Volume

55

Issue

6

fYear

2008

fDate

6/1/2008 12:00:00 AM

Firstpage

1511

Lastpage

1518

Abstract

A novel two-transistor (2T) floating-body cell (FBC) for embedded-DRAM applications is proposed and demonstrated via device/circuit simulations using a process/physics-based compact model, with numerical-simulation support. Significant advantages of the 2T cell, in which the charged/discharged body of one transistor (1T) drives the gate of the other, over the currently popular 1T-DRAM FBC are noted and explained. Furthermore, a modification of the basic 2T-FBC structure, which in essence results in a floating-body/gate cell (FBGC), is shown to yield dramatic reduction in power dissipation in addition to better signal margin, longer data retention, and higher memory density. Design and processing issues that need to be addressed for optimal performance and for sustained FBGC viability in nanoscale CMOS are discussed.

Keywords

CMOS digital integrated circuits; DRAM chips; integrated circuit design; nanoelectronics; numerical analysis; charged-discharged body; higher memory density; low-power nanoscale embedded DRAM; nanoscale CMOS; numerical-simulation support; power dissipation; process-physics-based compact model; two-transistor floating-body-gate cell; CMOS technology; Capacitors; Circuit simulation; FinFETs; MOSFET circuits; Nanoscale devices; Numerical models; Partial discharges; Random access memory; Substrates; Capacitorless DRAM; GIDL current; SOI floating-body effects; charge dynamics; double-gate (DG) FinFETs;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2008.922796

Filename

4527064