• DocumentCode
    1228994
  • Title

    CAD flows for chip-package coverification

  • Author

    Varma, Ambrish K. ; Glaser, Alan ; Franzon, Paul D.

  • Author_Institution
    Electr. & Comput. Eng. Dept., North Carolina State Univ., Raleigh, NC
  • Volume
    28
  • Issue
    1
  • fYear
    2005
  • Firstpage
    96
  • Lastpage
    101
  • Abstract
    A unified method is presented for layout and package design implemented within a commercial design environment that will reduce design time and enable chip-package coverification
  • Keywords
    electronic design automation; formal verification; integrated circuit packaging; multichip modules; technology CAD (electronics); CAD flows; chip package codesign; chip-package coverification; commercial design environment; computer-aided design; design automation; design time reduction; multichip modules; package layout; system in package; unified method; Delay; Design automation; Integrated circuit packaging; Multichip modules; Radio frequency; Routing; Semiconductor device packaging; System-on-a-chip; Timing; User interfaces; Chip package codesign; computer-aided design; design automation; multichip modules (MCMs); system in package (SIP);
  • fLanguage
    English
  • Journal_Title
    Advanced Packaging, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1521-3323
  • Type

    jour

  • DOI
    10.1109/TADVP.2004.841475
  • Filename
    1391072
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1228994