Title :
Low-Complexity Link Microarchitecture for Mesochronous Communication in Networks-on-Chip
Author :
Vitullo, Francesco ; Insalata, Nicola E L ; Petri, Esa ; Saponara, Sergio ; Fanucci, Luca ; Casula, Michele ; Locatelli, Riccardo ; Coppola, Marcello
Author_Institution :
Dept. of Inf. Eng., Univ. of Pisa, Pisa
Abstract :
Clock distribution is an important issue when designing Multi Processor Systems-on-Chip on deep sub-micron technology nodes and non-synchronous approaches are becoming popular in this field. This work presents a low-complexity link microarchitecture for mesochronous on-chip communication that enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. With respect to the state of the art, the proposed link architecture stands for its low power and low complexity overheads; moreover it can be easily integrated in a conventional digital design flow since it is implemented by means of standard cells only. Results are presented referring to the link integrated within a Multi Processor tiled architecture based on a Network-on-Chip communication backbone on a CMOS 65 nm technology
Keywords :
network-on-chip; back-end turnarounds; clock distribution; clock tree synthesis; deep submicron technology nodes; low complexity link microarchitecture; mesochronous on-chip communication; multi processor systems-on-chip; network-on-chip communication; networks-on-chip; power consumption reduction; size 65 nm; CMOS process; CMOS technology; Clocks; Energy consumption; Frequency synthesizers; Microarchitecture; Network synthesis; Network-on-a-chip; Process design; Spine; Architecture; Asynchronous/synchronous operation; Low-power design; Multiprocessor Systems; On-chip interconnection networks; Register-Transfer-Level Implementation; Standard cells; VLSI; VLSI Systems;
Journal_Title :
Computers, IEEE Transactions on
