A novel method for worst-case interconnect delay estimation

Author

Chen, Bin ; Yang, Huazhong ; Luo, Rong ; Wang, Hui

Author_Institution

Dept. of Electron. & Eng., Tsinghua Univ., Beijing, China

Volume

50

Issue

6

fYear

2003

fDate

6/1/2003 12:00:00 AM

Firstpage

778

Lastpage

781

Abstract

This brief presents a novel low-complexity crosstalk-aware method to estimate the worst-case interconnect delay. By regarding the RC network as a modified two-pole linear time-invariant system and taking the skew of aggressive signals into consideration, the worst-case delay estimated by the proposed method is approximately 5% different from the results by HSPICE.

Keywords

Newton-Raphson method; RC circuits; SPICE; crosstalk; delay estimation; integrated circuit interconnections; integrated circuit modelling; integrated circuit noise; HSPICE; Newton-Raphson method; RC network; aggressive signal skew; deep-submicron integrated circuit technology; low-complexity crosstalk-aware method; modified two-pole linear time-invariant system; moment matching; peak noise; worst-case interconnect delay estimation; Capacitance; Capacitors; Circuit noise; Coupling circuits; Crosstalk; Delay estimation; Integrated circuit interconnections; Integrated circuit noise; Switches; Very large scale integration;

fLanguage

English

Journal_Title

Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on

Publisher

ieee

ISSN

1057-7122

Type

jour

DOI

10.1109/TCSI.2003.812619

Filename

1208621