Exploiting static and dynamic locality of timing errors in robust L1 cache design

The Process-Variation (PV) effect is a major reliability concern in semiconductor industry as the technology node continues shrinking. As the crucial component in modern processors, cache is vulnerable to PV-induced timing-errors due to its large scale while low logic path depth. To tolerate this timing-error in cache, asymmetric pipelining has been employed, which has low implementation costs while induces unnecessary latency overhead thus degrades the performance of the whole processor. In this paper, we proposes a novel approach to apply variable latency in L1 cache access thus significantly reduce the performance overhead in tolerating the PV-induced timing-errors. Our results show that the performance loss of our approach on processors with low, medium and high error_rate L1 cache is 0.1%, 1.5% and 3.5%, respectively. While the area and power overhead of our approach is 3.1% and 2.8%.