• DocumentCode
    123033
  • Title

    An application-aware heterogeneous prioritization framework for NoC based chip multiprocessors

  • Author

    Pimpalkhute, Tejasi ; Pasricha, Sudeep

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Colorado State Univ., Fort Collins, CO, USA
  • fYear
    2014
  • fDate
    3-5 March 2014
  • Firstpage
    76
  • Lastpage
    83
  • Abstract
    In chip multiprocessor (CMP) systems with multi-application workloads, communication and memory access both play an important role in influencing system performance. Intelligently prioritizing network packets and memory requests can notably improve system throughput. But with increasing workload diversity in CMPs, applying the same request prioritization rules across the chip can lead to sub-optimal results. In this paper, we propose a novel heterogeneous prioritization framework for CMPs in which two different packet prioritization approaches are proposed and applied to network-on-chip (NoC) routers. A new ranking scheme for classifying an application´s criticality is also proposed. We evaluate our framework using a detailed cycle-accurate full system event-driven simulator. Our experimental results show that the proposed framework outperforms fair prioritization techniques by up to 12.6% as well as other application-specific techniques from prior literature by up to 6.9% for various multi-application workloads.
  • Keywords
    multiprocessing systems; network routing; network-on-chip; CMP systems; NoC routers; NoC-based chip multiprocessors; application-aware heterogeneous prioritization framework; application-specific technique; detailed cycle-accurate full-system event-driven simulator; fair prioritization technique; memory access; memory requests; multiapplication workloads; network packets; network-on-chip routers; packet prioritization approach; request prioritization rules; workload diversity; Indexes; Measurement; Network interfaces; Parallel processing; Ports (Computers); Radiation detectors; Throughput; Network-on-chip; memory level parallelism; memory-aware prioritization; network packet prioritization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ISQED), 2014 15th International Symposium on
  • Conference_Location
    Santa Clara, CA
  • Print_ISBN
    978-1-4799-3945-9
  • Type

    conf

  • DOI
    10.1109/ISQED.2014.6783309
  • Filename
    6783309