Title :
Planar Microspring—A Novel Compliant Chip-to-Package Interconnect for Wafer-Level Packaging
Author :
Liao, E.B. ; Tay, Andrew A O ; Ang, Simon S T ; Feng, H.H. ; Nagarajan, R. ; Kripesh, V. ; Kumar, R. ; Lo, G.Q.
Author_Institution :
Inst. of Microelectron., Singapore
fDate :
5/1/2009 12:00:00 AM
Abstract :
In this paper, a novel compliant chip-to-package interconnect, planar microspring, is presented in terms of design consideration, wafer-level fabrication process and mechanical characterization. Several spring designs have been evaluated, and results indicate that a J-shaped spring design produces a combination of high 3D compliances and acceptable electrical parasitics. Further, numerical analyses on the J -shaped microspring interconnect examined the dependence of mechanical and electrical performance upon geometry parameters. A wafer-level fabrication flow combining complementary metal oxide semiconductor (CMOS) back-end-of-line (BEOL) process and 3-D surface micromachining technique has been successfully implemented to create planar microspring interconnect prototypes with a fine pitch (100 mum). The mechanical robustness of the prototype interconnects have been evaluated by nanoindentation. Finally, high-frequency electrical simulation suggested that the interconnect application can be extended up to ~35 GHz without significant power loss.
Keywords :
CMOS integrated circuits; electronics packaging; integrated circuit interconnections; micromachining; nanoindentation; 3D surface micromachining; CMOS back-end-of-line process; J-shaped spring design; chip-to-package interconnect; complementary metal oxide semiconductor; high-frequency electrical simulation; nanoindentation; planar microspring; wafer-level fabrication flow; wafer-level packaging; $S$-parameter; Benzocyclobutene (BCB); compliance; electrical parasitic; planar microspring interconnect; wafer-level packaging;
Journal_Title :
Advanced Packaging, IEEE Transactions on
DOI :
10.1109/TADVP.2008.924247