Design of an analogue subthreshold multiplier suitable for implementing an artificial neural network

Describes work undertaken as a final-year undergraduate project and considers the design of an analogue VLSI implementation of the multi-layer perceptron artificial neural network. The network is principally composed of multipliers, and therefore the design effort concentrated on the development of a space-efficient multiplier. The circuit exploits the subthreshold region of operation of a MOSFET and it was necessary to examine in detail the modelling of this region of operation. In the course of the work, design tools made available under the ECAD initiative were used; in particular, the circuit simulator HSPICE was used for parameter extraction, in an unconventional way, to great advantage