• DocumentCode
    123110
  • Title

    A parallel clustering algorithm for placement

  • Author

    Momeni, Ahmadreza ; Mistry, Perhaad ; Kaeli, David

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA
  • fYear
    2014
  • fDate
    3-5 March 2014
  • Firstpage
    349
  • Lastpage
    356
  • Abstract
    In order to improve the layout quality of a VLSI design, many placement tools employ clustering algorithms to prune the optimization space and produce a design that can be enhanced while considering multiple design constraints. An intelligent clustering algorithm can guide a placement tool to reduce wire length, reduce cycle time, consider additional metrics or optimize a design based on a combination of these objectives. Given the myriad of choices, clustering algorithms can be time consuming to run, and this can impact our ability to fully explore the clustering space. Heterogeneous systems have been growing in popularity due to their attractive processing capabilities. Heterogeneous computing systems can be leveraged to improve the performance of clustering algorithms. In this paper, we present an OpenCL-based parallel clustering algorithm used during placement that targets heterogeneous systems. Our algorithm splits the computation, and exploits both CPU and GPU concurrently to balance the memory usage and the computational load in the heterogeneous system. We compare our parallel algorithm CL-Choice to a number of previously proposed algorithms. We evaluate these implementations in terms of placement speed and overall design quality. Simulation results show that our parallel implementation run on a Graphics Processing Unit (GPU) can achieve a 27× improvement over a number of serial algorithms in terms of speed, while not significantly impacting design quality.
  • Keywords
    VLSI; circuit analysis computing; graphics processing units; integrated circuit design; parallel algorithms; pattern clustering; CPU; GPU; OpenCL-based parallel clustering algorithm; VLSI design; cycle time reduction; design quality; graphics processing unit; heterogeneous computing systems; intelligent clustering algorithm; multiple design constraints; optimization space; parallel algorithm CL-choice; placement tools; serial algorithms; wire length reduction; Algorithm design and analysis; Benchmark testing; Clustering algorithms; Graphics processing units; Kernel; Merging; Very large scale integration; Clustering; GPU; OpenCL; Parallel; Placement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality Electronic Design (ISQED), 2014 15th International Symposium on
  • Conference_Location
    Santa Clara, CA
  • Print_ISBN
    978-1-4799-3945-9
  • Type

    conf

  • DOI
    10.1109/ISQED.2014.6783347
  • Filename
    6783347