Models of access delays in multiprocessor memories

The performance of an interleaved common memory accessed uniformly by multiple processors is modeled by queuing and simulation methods. The model includes access conflicts at the bank level while assuming an ideal access network. A general scaling law is derived that indicates that memory access delays are given by the product of the bank reservation time and a function of the memory utilization, which is the average number of access requests arriving at a bank per bank reservation time. For light, uniform memory traffic. access delays are proportional to the square of the bank reservation time and to the ratio of the number of active memory access streams to the number of memory banks. With an assumption of random access patterns, an open and a closed queuing model are developed. To model pipelined access operations a new negative feedback model is introduced that includes the open and the closed models as special cases and is also well suited for modeling linked access streams. Delay dependence on bank reservation time is quadratic for light loads and linear for very heavy loads. The queuing models are validated by simulations