Compiler-directed leakage energy reduction for instruction scratch-pad memories

Scratch-Pad Memories (SPMs) have been increasingly used in embedded systems, for which it is important to reduce the leakage energy consumption. While there are several techniques to reduce the leakage energy for cache memories, those techniques may result in significant performance overheads for instruction SPMs. In this paper, we study a compiler-based approach to reducing the instruction SPM leakage energy efficiently, which can also minimize the performance overhead. Our evaluation indicates that the compiler-based approach is superior to periodical or bank-based methods, all of which use drowsy techniques. On average, the compiler-based method can reduce the SPM leakage energy by nearly 89.82%, with only 0.25% performance overhead.