Analysis of metastable operation in D latches

Clocked D-latches commonly form the core of more complex circuits used for synchronization. To account for the unusual output voltage waveforms these components exhibit while in a metastable state, the conventional propagation delay time definition is modified. The critical input timing for which metastable operation occurs is defined, and the mean time between failures (MTBF) of the latch due to metastable operation is derived as a function of this critical input timing. Estimation of the critical input timing is based on a detailed analysis of the initialization and resolving phases of metastable operation in an nMOS D latch