DocumentCode
1231396
Title
Calculating the FHT in hardware
Author
Erickson, Adam C. ; Fagin, Barry S.
Author_Institution
Sequoia Systems Inc., Marlboro, MA, USA
Volume
40
Issue
6
fYear
1992
fDate
6/1/1992 12:00:00 AM
Firstpage
1341
Lastpage
1353
Abstract
A parallel, pipelined architecture for calculating the fast Hartley transform (FHT) is discussed. Hardware implementation of the FHT introduces two challenges: retrograde indexing and data scaling. A novel addressing scheme that permits the fast computation of FHT butterflies is proposed, and a hardware implementation of conditional block floating point scaling that reduces error due to data growth with little extra cost is described. Simulations reveal a processor capable of transforming a 1 K-point sequence in 170 μs using a 15.4 MHz clock
Keywords
computerised signal processing; digital arithmetic; parallel architectures; pipeline processing; transforms; 15.4 MHz; 170 mus; FHT butterflies; addressing scheme; conditional block floating point scaling; data growth error; data scaling; digital arithmetic; fast Hartley transform; fast computation; hardware implementation; parallel pipelined architecture; retrograde indexing; Clocks; Computational modeling; Convolution; Costs; Data mining; Discrete transforms; Hardware; Helium; Indexing; Performance gain;
fLanguage
English
Journal_Title
Signal Processing, IEEE Transactions on
Publisher
ieee
ISSN
1053-587X
Type
jour
DOI
10.1109/78.139240
Filename
139240
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