Title :
The iCore 520-MHz synthesisable CPU core
Author :
Richardson, Nick ; Huang, Lun Bin ; Hossain, Razak ; Lewis, Julian ; Zounes, Tommy ; Soni, Naresh
Author_Institution :
STMicroelectronics, San Diego, CA, USA
Abstract :
A new implementation of the ST20-C2 CPU architecture involves an eight-stage pipeline with hardware support to execute up to three instructions per cycle. The design operates up to 520 MHz at 1.8V, among the highest reported speeds for a synthesized CPU core.
Keywords :
cache storage; instruction sets; integrated circuit testing; microprocessor chips; parallel architectures; pipeline processing; 520 MHz; CPU architecture; ST20-C2 architecture; cache subsystem; data forwarding; iCore processor; instruction folding; pipeline microarchitecture; register scoreboards; synthesisable CPU core; Application specific integrated circuits; Central Processing Unit; Computer architecture; Decoding; Delay; Frequency measurement; Hardware; Microarchitecture; Pipelines; Registers;
Journal_Title :
Micro, IEEE
DOI :
10.1109/MM.2003.1209466
