NOLO: A no-loop, predictive useful skew methodology for improved timing in IC implementation

Useful skew is a well-known design technique that adjusts clock sink latencies to improve performance and/or robustness of highperformance IC designs. Current design methodologies apply useful skew after the netlist has been synthesized (e.g., with a uniform skew or clock uncertainty assumption on all flops), and after placement has been performed. However, the useful skew optimization is constrained by the zero-skew assumptions that are baked into previous implementation steps. Previous work of Wang et al. [15] proposes to break this chicken-egg quandary by back-annotating post-placement useful skews to a re-synthesis step (and, this loop can be repeated several times). However, it is practically infeasible to make multiple iterations through re-synthesis and physical implementation, as even the time for placement alone of a large hard macro block in a 28nm SOC can be five days [10]. Thus, in our work we seek a predictive, one-pass means of addressing the chicken-egg problem for useful skew. We observe that in a typical chip implementation flow, timing slacks at post-synthesis stage do not correlate well with timing slacks at postrouting stage. However, the correlation is improved when useful skew is applied at the post-synthesis stage. Based on this observation, we propose NOLO, a simple, “no-loop” predictive useful skew flow that applies useful skew at post-synthesis within a one-pass chip implementation. Further, our predictive useful skew flow can exploit an additional synthesis run to improve circuit timing without any turnaround time impact (two synthesis steps are run in parallel). Experimental results in a 28nm FDSOI technology show that our predictive useful flow can reduce runtime by 66% and improve total negative slack by 5% compared to the useful skew back-annotation flow of [15].