Title :
Sense Amplifier Pass Transistor Logic for energy efficient and DPA-resistant AES circuit
Author :
Khatir, M. ; Nazhandali, Leyla
Author_Institution :
Bradley Dept. of Electr. & Comput. Eng., Virginia Tech., Blacksburg, VA, USA
Abstract :
In this paper, we show that Sense Amplifier Pass Transistor Logic (SAPTL) is a promising choice for increasing Differential Power Analysis attack (DPA-attack) resistance while maintaining energy efficiency. Furthermore, we present an automatic approach to generate big SAPTL logic blocks (e.g. SBOX) from a synthesized verilog code. We have mounted differential power analysis attacks on the designed circuits and calculated the success rate over different noise conditions. Our results show that SAPTL consumes comparable amount of energy with respect to static CMOS while significantly improving resistance to power side channel attacks.
Keywords :
CMOS integrated circuits; cryptography; DPA-resistant AES circuit; SAPTL logic blocks; SBOX; Verilog code synthesis; differential power analysis attack resistance; energy efficient circuit; noise conditions; power side channel attacks; sense amplifier pass transistor logic; static CMOS; CMOS integrated circuits; Energy consumption; Logic gates; Power demand; Resistance; Semiconductor device modeling; Transistors; Differential Power Analysis (DPA) Attack; Energy Efficiency; Sense Amplifier Pass Transistor Logic (SAPTL);
Conference_Titel :
Quality Electronic Design (ISQED), 2014 15th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4799-3945-9
DOI :
10.1109/ISQED.2014.6783370
