Defect-Tolerant CMOL Cell Assignment via Satisfiability

We present a novel CAD approach to cell assignment of CMOL, a hybrid CMOS/molecular circuit architecture. Our method transforms any logically synthesized circuit based on AND/OR/NOT gates to a NOR gate circuit and maps the NOR gates to CMOL. We encode the CMOL cell assignment problem as Boolean conditions. The Boolean constraints are satisfiable if and only if there exists a solution to map all the NOR gates to the CMOL cells. We further investigate various types of static defects for the CMOL architecture and propose a reconfiguration technique that can deal with these defects. We introduce a new CMOL static defect model and provide an automated solution for CMOL cell assignment. Experiments show that our approach can result in smaller area (CMOL cell usage) and better timing delay than prior approach.