Rapid prototype and implementation of a high-throughput and flexible FFT ASIP based on LISA 2.0

This paper presents a highly efficient machine description language LISA for application specific instruction-set processor (ASIP) architecture exploration, software tools design, system verification and design implementation. The proposed design flow enables a rapid prototyping and evaluation of different architectures, reduces the design time and human effort with regard to traditional design methodologies. A case study for parallel FFT algorithm is demonstrated in this work. We proposed a scalable butterfly processing structure with fixed shuffling mode between stages. Besides, resource sharing and an efficient vector address generation mechanism are adopted to reduce the hardware complexity and power dissipation. Simulation and synthesis results show that our FFT-ASIP achieves a higher energy-efficiency and flexibility than other works, and the area cost is low.