An efficient two´s complement systolic multiplier for real-time digital signal processing

The authors propose a fast, area-efficient, bit-parallel systolic architecture for two´s complement multiplication, which can be implemented on a single VLSI chip. This architecture is more efficient than other reported bit-parallel architectures in terms of performance and utilization of silicon area. The bit cells are arranged in a 2-D array which enhances the extensibility and provides efficiency for high-precision data. Barrel shifters are employed on the cell level instead of a basic full adder, which increases the throughput rate by a factor of three over the other reported pipeline structures. The structure is highly regular and programmable, and it can be adapted to the requirements of different digital signal processing applications without significant loss in throughput and efficiency