Analysis of the System Level Design of a 1.5 Bit/Stage Pipeline ADC

Author

Tripathi, Arvind K. ; Singhal, Roshani ; Verma, A.

Author_Institution

Noida Inst. of Eng. & Technol., Noida, India

fYear

2014

fDate

8-9 Feb. 2014

Firstpage

89

Lastpage

94

Abstract

In this paper a comparison of analog versus digital information is given, where the superior noise resilience of digital signals is shown to necessitate digital signalling for modern high-speed signaling environments. Non-idealities that are analog in nature are shown to necessitate ADCs in the digital signal path, which allow for signal recovery in the digital domain. A brief discussion of the Flash ADC is given, followed by a detailed analysis of the system level design of a 1.5 bit/stage pipeline ADC.

Keywords

analogue-digital conversion; digital communication; digital signal processing chips; flash memories; pipeline processing; signal denoising; digital domain; digital signal processing; digital signalling; flash ADC; modern high-speed signaling; noise resilience; pipeline ADC; signal recovery; system level design analysis; Accuracy; Clocks; Error correction; Noise; Pipelines; Receivers; Transfer functions; FOM; error correction; pipelining; power scaling;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Computing & Communication Technologies (ACCT), 2014 Fourth International Conference on

Conference_Location

Rohtak

Type

conf

DOI

10.1109/ACCT.2014.96

Filename

6783432