DocumentCode :
1232754
Title :
Robustness of a selective epitaxial-growth process of silicon and its application to the fabrication of a high-quality hybrid SOI wafer
Author :
Nagano, Hajime ; Miyano, Kiyotaka ; Yamada, Takashi ; Mizushima, Ichiro
Author_Institution :
Process & Manuf. Eng. Center, Toshiba Corp., Yokohama, Japan
Volume :
18
Issue :
1
fYear :
2005
Firstpage :
13
Lastpage :
18
Abstract :
Robustness of a selective epitaxial growth of silicon is demonstrated. The process window of selectivity was estimated quantitatively using the Taguchi method and signal-to-noise ratio analysis for the first time. Both the number of the silicon nuclei on the mask layer and the growth rate of silicon on a silicon substrate were investigated as the output parameters of the Taguchi method. One of the most effective process parameters for the suppression of silicon nucleation on the mask layer without retarding the growth rate of silicon is revealed to be the flow rate of SiH2Cl2. By calculating the number of the silicon nuclei, which could not be detected by an available measurement method, the process window of the selectivity could be determined with which a wafer with selective epitaxial silicon layer having LSI-quality could be fabricated. A high-quality silicon-on-insulator (SOI) wafer that has both an SOI region and bulk-silicon region can be obtained, and a high-quality embedded device could be realized on the SOI wafer.
Keywords :
Taguchi methods; elemental semiconductors; epitaxial growth; masks; semiconductor epitaxial layers; semiconductor growth; silicon; silicon-on-insulator; substrates; SOI region; Si; SiH2Cl2 flow rate; Taguchi method; bulk silicon region; high quality embedded device; high quality hybrid SOI wafer fabrication; mask layer; process parameters; process window; robustness; selective epitaxial growth process; signal-to-noise ratio analysis; silicon growth rate; silicon nucleation; silicon nuclei; silicon substrate; Epitaxial growth; Fabrication; Nuclear measurements; Random access memory; Robustness; Signal analysis; Signal to noise ratio; Silicon on insulator technology; Substrates; System-on-a-chip;
fLanguage :
English
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
Publisher :
ieee
ISSN :
0894-6507
Type :
jour
DOI :
10.1109/TSM.2004.841818
Filename :
1393039
Link To Document :
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