Ground bounce in digital VLSI circuits

Author

Heydari, Payam ; Pedram, Massoud

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of California, Irvine, CA, USA

Volume

11

Issue

2

fYear

2003

fDate

4/1/2003 12:00:00 AM

Firstpage

180

Lastpage

193

Abstract

This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the propagation delay and the optimum tapering factor of a multistage buffer is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. Effect of an on-chip decoupling capacitor on the ground bounce waveform and circuit speed is analyzed next and a closed form expression for the peak value of the differential-mode component of the ground bounce in terms of the on-chip decoupling capacitor is provided. Finally, a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented.

Keywords

CMOS digital integrated circuits; VLSI; integrated circuit modelling; analytical model; chip-package interface parasitics; design method; digital CMOS VLSI circuit; ground bounce; on-chip decoupling capacitor; optimization; output driver; propagation delay; short-channel MOS device; signal integrity; switching time; tapered buffer; CMOS digital integrated circuits; Circuit analysis; Design methodology; Driver circuits; MOS capacitors; MOS devices; Propagation delay; Semiconductor device modeling; Switched capacitor circuits; Very large scale integration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2003.810785

Filename

1210499