An Arithmetic and Logic Unit Optimized for Area and Power

This paper presents a design of a 4-bit arithmetic logic unit (ALU) by taking vantage of the concept of gate diffusion input (GDI) technique. ALU is the most crucial and core component of central processing unit as well as of numbers of embedded system and microprocessors. In this, ALU consists of 4×1 multiplexer, 2×1 multiplexer and full adder designed to implements logic operations, such as AND, OR, etc. and arithmetic operations, as ADD and SUBTRACT. GDI cells are used in the design of multiplexers and full adder which are then associated to realize ALU. The simulation is carried out Tanner EDA 13.0 simulator using TSMC BSIM 250nm technologies and compared with previous designs realized with Pass transistor logic and CMOS logic. The simulation shows that the design is more efficient with less power consumption, less surface area and is faster as compared to pass transistor and CMOS techniques.