A low-power silicon on sapphire CMOS optoelectronic receiver using low- and high-threshold devices

Author

Apsel, Alyssa B. ; Andreou, Andreas G.

Author_Institution

Cornell Univ., Ithaca, NY, USA

Volume

52

Issue

2

fYear

2005

Firstpage

253

Lastpage

261

Abstract

We report on the architecture and experimental characterization of a small-footprint optoelectronic receiver for parallel arrays of optical interconnects. The receiver is designed and fabricated in the 0.5-μm silicon on sapphire CMOS technology. The circuit design exploits the properties of MOS transistors with three different threshold voltages and the insulating substrate to achieve a low-power, high-speed and compact circuit. The design attains a 7-pJ energy per bit transduction cost when operated at 1 Gbit/s data rates.

Keywords

CMOS integrated circuits; network synthesis; optical interconnections; optoelectronic devices; sapphire; silicon; silicon-on-insulator; 0.5 micron; CMOS technology; MOS transistors; Si; chip to chip communication; circuit design; high-threshold devices; insulating substrate; low-threshold devices; optical interconnects; optoelectronic receiver; parallel arrays; silicon on sapphire CMOS; silicon-on-insulators CMOS; threshold voltages; transduction cost; CMOS technology; Circuit synthesis; Costs; Insulation; MOSFETs; Optical arrays; Optical interconnections; Optical receivers; Silicon on insulator technology; Threshold voltage; Chip-to-chip communication; optical interconnect; optoelectronic receiver; silicon on sapphire (SOS) CMOS; silicon-on-insulators (SOI) CMOS;

fLanguage

English

Journal_Title

Circuits and Systems I: Regular Papers, IEEE Transactions on

Publisher

ieee

ISSN

1549-8328

Type

jour

DOI

10.1109/TCSI.2004.840289

Filename

1393158