Analysis of the specific on-resistance of vertical high-voltage DMOSFETs on SOI

Author

Heinle, Ulrich ; Olsson, Jörgen

Author_Institution

Angstrom Lab., Uppsala Univ., Sweden

Volume

50

Issue

5

fYear

2003

fDate

5/1/2003 12:00:00 AM

Firstpage

1416

Lastpage

1419

Abstract

Integration of high-voltage devices on SOI substrates with deep trench isolation offers the possibility to combine low-voltage circuitry and high-voltage devices on the same chip. However, due to the buried oxide, all device contacts have to be on top of the silicon. Consequently the on-resistance does not scale in the same manner as for conventional vertical devices. In this paper, an analytical model is developed, which accurately predicts the specific on-resistance and its dependency on the number of cells. It is shown that the model predicts an optimum number of cells for a minimal specific on-resistance.

Keywords

isolation technology; power MOSFET; semiconductor device models; silicon-on-insulator; 500 V; SOI substrates; analytical model; buried oxide; deep trench isolation; high-voltage devices; low-voltage circuitry; optimum number of cells; specific on-resistance; vertical high-voltage DMOSFETs; Analytical models; Automotive electronics; Circuits; Dielectric substrates; Leakage current; Power system modeling; Predictive models; Robust control; Silicon on insulator technology; Voltage;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2003.813458

Filename

1210815