Technique to Reduce the Resolution Requirement of Digitally Controlled Oscillators for Digital PLLs

Author

Hsieh, Ping-Hsuan ; Yang, Chih-Kong Ken

Author_Institution

Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA

Volume

54

Issue

3

fYear

2007

fDate

3/1/2007 12:00:00 AM

Firstpage

237

Lastpage

241

Abstract

Phase-locked loops (PLLs) are a critical component in modern systems. Digital PLLs (DPLLs) are increasingly popular in CMOS technologies due to their ease of integration and scalability with digital logic. However, digital quantization results in larger steady-state systematic jitter, or dithering. High resolution is needed to control the oscillator to minimize the dithering. This brief proposes a simple method to reduce the frequency-resolution requirement. The method allows for substantial reduction in the hardware complexity without sacrificing the DPLL´s dynamic characteristics

Keywords

CMOS digital integrated circuits; circuit noise; digital phase locked loops; jitter; logic circuits; oscillators; quantisation (signal); CMOS technologies; digital logic; digital phase-locked loops; digital quantization; digitally controlled oscillators; steady-state systematic jitter; CMOS logic circuits; CMOS technology; Digital control; Frequency; Jitter; Oscillators; Phase locked loops; Quantization; Scalability; Steady-state; Digital quantization; frequency-resolution requirement; phase-locked loops (PLLs); systematic jitter;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2006.889458

Filename

4132960