Title : 
New Systolic Algorithm and Array Architecture for Prime-Length Discrete Sine Transform
         
        
            Author : 
Meher, Pramod Kumar ; Swamy, M.N.S.
         
        
            Author_Institution : 
Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore
         
        
        
        
        
            fDate : 
3/1/2007 12:00:00 AM
         
        
        
        
            Abstract : 
Using a simple input-regeneration approach and index-transformation techniques, a new formulation is presented in this paper for computing an N-point prime-length discrete sine transform (DST) through two pairs of [(N-1)/4]-point cyclic convolutions, where [(N-1)/4] is an odd number. The cyclic convolution-based algorithm is used further to obtain a simple regular and locally connected linear systolic array for concurrent pipelined implementation of the DST. It is shown that the proposed systolic structure involves significantly less area-time complexity compared with that of the existing structures
         
        
            Keywords : 
VLSI; computational complexity; convolution; discrete transforms; systolic arrays; area-time complexity; array architecture; cyclic convolution-based algorithm; discrete cosine transform; index-transformation techniques; input-regeneration approach; linear systolic array; prime-length discrete sine transform; systolic algorithm; very large scale integration; Computer architecture; Convolution; Convolutional codes; Discrete cosine transforms; Discrete transforms; Hardware; Signal processing; Systolic arrays; Transform coding; Very large scale integration; Discrete cosine transform (DCT); discrete sine transform (DST); systolic array; very large scale integration (VLSI);
         
        
        
            Journal_Title : 
Circuits and Systems II: Express Briefs, IEEE Transactions on
         
        
        
        
        
            DOI : 
10.1109/TCSII.2006.889453