3.9 ps SiGe HBT ECL ring oscillator and transistor design for minimum gate delay

Author

Jagannathan, Basanth ; Meghelli, Mounir ; Chan, Kevin ; Rieh, Jae-Sung ; Schonenberg, Kathryn ; Ahlgren, David ; Subbanna, Seshadri ; Freeman, Greg

Author_Institution

IBM Microelectron. Semicond. R&D Center, Hopewell Junction, NY, USA

Volume

24

Issue

5

fYear

2003

fDate

5/1/2003 12:00:00 AM

Firstpage

324

Lastpage

326

Abstract

We show empirical results that demonstrate the effect of high performance SiGe HBT design parameters on the minimum gate delay of an ECL ring oscillator. SiGe HBT devices with a high f/sub MAX/ (338 GHz) and a low f/sub T/ (180 GHz) achieve a minimum delay of 3.9 ps, which to our knowledge is the lowest reported delay for a silicon based logic gate. Compared to the extracted (extrapolated) f/sub T/ and f/sub MAX/, a simple figure of merit proportional to /spl radic/f/sub T//R/sub B/C/sub CB/ with R/sub B/ and C/sub CB/ extracted from S-parameter measurement is best correlated to the minimum gate delay.

Keywords

Ge-Si alloys; bipolar logic circuits; delays; emitter-coupled logic; heterojunction bipolar transistors; high-speed integrated circuits; logic gates; oscillators; semiconductor materials; 180 GHz; 3.9 ps; 338 GHz; Si based logic gate; SiGe; SiGe HBT ECL ring oscillator; SiGe HBT design parameters; high-speed devices; minimum gate delay; Circuits; Delay effects; Germanium silicon alloys; Heterojunction bipolar transistors; Logic devices; Logic gates; Ring oscillators; Silicon germanium; Space technology; Temperature;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2003.812568

Filename

1210841