• DocumentCode
    1234379
  • Title

    Implementation of iterative networks with CMOS differential logic

  • Author

    Lu, Shih-Lien

  • Author_Institution
    Univ. of Southern California, Los Angeles, CA, USA
  • Volume
    23
  • Issue
    4
  • fYear
    1988
  • fDate
    8/1/1988 12:00:00 AM
  • Firstpage
    1013
  • Lastpage
    1017
  • Abstract
    An improved differential CMOS logic family called enabled/disabled CMOS differential logic (ECDL) is presented. An extension to this logic technique which enables the implementation of iterative network arrays is also presented. Two simple logic functions, a Gray-to-binary decoder and an XOR cell, are implemented to demonstrate this methodology
  • Keywords
    CMOS integrated circuits; cellular arrays; integrated logic circuits; iterated switching networks; CMOS differential logic; ECDL; Gray-to-binary decoder; XOR cell; enabled/disabled CMOS differential logic; iterative network arrays; CMOS logic circuits; CMOS technology; Delay; Gallium arsenide; Intelligent networks; Josephson junctions; Logic functions; Power dissipation; Solid state circuits; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/4.354
  • Filename
    354
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1234379