Title :
Implementation of iterative networks with CMOS differential logic
Author_Institution :
Univ. of Southern California, Los Angeles, CA, USA
fDate :
8/1/1988 12:00:00 AM
Abstract :
An improved differential CMOS logic family called enabled/disabled CMOS differential logic (ECDL) is presented. An extension to this logic technique which enables the implementation of iterative network arrays is also presented. Two simple logic functions, a Gray-to-binary decoder and an XOR cell, are implemented to demonstrate this methodology
Keywords :
CMOS integrated circuits; cellular arrays; integrated logic circuits; iterated switching networks; CMOS differential logic; ECDL; Gray-to-binary decoder; XOR cell; enabled/disabled CMOS differential logic; iterative network arrays; CMOS logic circuits; CMOS technology; Delay; Gallium arsenide; Intelligent networks; Josephson junctions; Logic functions; Power dissipation; Solid state circuits; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
