Title :
A fast bipolar-valued inner product processor chip for associative memory networks
Author :
Wang, Chua-Chin ; Hsueh, Ya-Hsin ; Hunng, Chenn-Jung
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fDate :
7/1/2003 12:00:00 AM
Abstract :
In this work, a novel and high-speed realization of bipolar-valued inner product processor for associative memory networks is presented, wherein the treatment of inner product of two bipolar vectors is given. Besides, a systolic architecture of digital compressors is used to reduce the carry propagation delay in the critical path of the inner product of two bipolar vectors.
Keywords :
CMOS digital integrated circuits; content-addressable storage; coprocessors; high-speed integrated circuits; systolic arrays; associative memory networks; bipolar-valued inner product processor; carry propagation delay; digital compressors; high-speed realization; systolic architecture; Associative memory; Chaos; Circuits; Compressors; Computer architecture; Computer networks; Pattern recognition; Propagation delay; Prototypes; Speech coding;
Journal_Title :
Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on
DOI :
10.1109/TCSI.2003.813972
