Title :
An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation
Author :
Jun, Young-Hyun ; Ki Jun ; Park, Song-Bai
Author_Institution :
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fDate :
9/1/1989 12:00:00 AM
Abstract :
A delay model for multiple delay simulation for NMOS and CMOS logic circuits is proposed. For the simple inverter the rise or fall delay time is approximated by a product of polynomials of the input waveform slope, the output loading capacitance, and the device configuration ratio, with the polynomial coefficients determined so as to best fit the SPICE simulation results for a given fabrication process. This approach can easily be extended to the case of multiple-input transitions. The simulation results show that the proposed modes can predict the delay times within 5% error and with a speedup of three orders of magnitude for several circuits tested as compared with the SPICE simulation
Keywords :
CMOS integrated circuits; MOS integrated circuits; circuit analysis computing; delays; integrated logic circuits; polynomials; CMOS; MOS logic circuits; NMOS; computer aided analysis; delay time modeling; device configuration ratio; input waveform slope; multiple delay simulation; multiple-input transitions; output loading capacitance; polynomial approximation; polynomial coefficients; CMOS logic circuits; Circuit simulation; Circuit testing; Delay effects; Logic devices; MOS devices; Polynomials; Predictive models; SPICE; Semiconductor device modeling;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
