Remote Triggered FPGA based Automated System

Engineering students cannot afford the expensive high-end FPGA kits to execute and test their designs. In such cases, the users can check their designs using simulation but it does not give a feel of running their designs on the actual system. So a remote triggered system allows the user to test their designs on high end FPGA kits. The remote system asks the user to provide the design file and the test vectors and the system abstracts the tasks of compiling, synthesizing, pin assignment etc as these are automated at the remote FPGA´s end or the server end. Thus, the users´ work is further simplified. Hence the name, Remote Triggered FPGA based Automated System. Such a system is developed under e-Prayog project at IIT Bombay as a part of Virtual Lab project, an initiative by Ministry of Human Resource Development (MHRD) under National Mission on Education through ICT. This paper presents the architecture of this system using an FSM method to implement it and also describes the supporting material developed to run a remote lab.