A 75-GHz Phase-Locked Loop in 90-nm CMOS Technology

Author

Lee, Jri ; Liu, Mingchung ; Wang, Huaide

Author_Institution

Electr. Eng. Dept., Nat. Taiwan Univ., Taipei

Volume

43

Issue

6

fYear

2008

fDate

6/1/2008 12:00:00 AM

Firstpage

1414

Lastpage

1426

Abstract

The design and experimental verification of a 75-GHz phase-locked loop (PLL) fabricated in 90-nm CMOS technology is presented. The circuit incorporates a three-quarter wavelength oscillator to achieve high-frequency operation and a novel phase-frequency detector (PFD) based on SSB mixers to suppress the reference feedthrough. The PLL demonstrates an operation range of 320 MHz and reference sidebands of less than -72 dBc while consuming 88 mW from a 1.45-V supply.

Keywords

CMOS integrated circuits; field effect MIMIC; millimetre wave mixers; millimetre wave oscillators; phase locked loops; CMOS technology; SSB mixers; frequency 75 GHz; phase-frequency detector; phase-locked loop; power 88 mW; reference feedthrough suppression; size 90 nm; voltage 1.45 V; wavelength oscillator; Amplitude modulation; CMOS technology; Circuit topology; Frequency conversion; Phase detection; Phase frequency detector; Phase locked loops; RLC circuits; Transceivers; Voltage-controlled oscillators; Frequency divider; phase and frequency detector (PFD); phase-locked loop (PLL); reference spurs; transmission line; voltage-controlled oscillator (VCO);

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2008.922719

Filename

4531674