An H.264 video decoder based on a latest generation DSP

Author

Pescador, F. ; Maturana, G. ; Garrido, M.J. ; Juarez, E. ; Sanz, C.

Author_Institution

Electron. & Microelectron. Design Group (GDEM), Univ. Politec. de Madrid, Madrid

Volume

55

Issue

1

fYear

2009

fDate

2/1/2009 12:00:00 AM

Firstpage

205

Lastpage

212

Abstract

Latest generation DSPs are becoming more efficient, being able to improve their forerunners while reducing their internal memory size to lower the cost. In this paper, an H.264 video decoder based on a latest generation DSP is described. Both the EDMA and the memory architecture of the processor have been fully exploited to increase the execution speed. Profiling tests have been carried out by using digital TV streams and DVD transcoded sequences. The speed of the new DSP running the decoder is 16% better than that of a forerunner with 20% more internal memory running the same decoder.

Keywords

digital signal processing chips; digital television; digital versatile discs; video codecs; DVD transcoded sequences; EDMA; H.264 video decoder; digital TV streams; digital signal processor; execution speed; memory architecture; Costs; Decoding; Digital TV; Digital signal processing; IEC standards; ISO standards; Memory architecture; Streaming media; Testing; Video coding; H264; Latest Generation DSP; Software Optimization; Video Decoder;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/TCE.2009.4814436

Filename

4814436