• DocumentCode
    1237048
  • Title

    A VLSI architecture for fast inversion in GF(2m)

  • Author

    Feng, Gui-liang

  • Author_Institution
    Shanghai Inst. of Comput. Technol., China
  • Volume
    38
  • Issue
    10
  • fYear
    1989
  • fDate
    10/1/1989 12:00:00 AM
  • Firstpage
    1383
  • Lastpage
    1386
  • Abstract
    A new algorithm for performing fast inversion in GF (2 m) is presented. The algorithm requires O[mlog2 m) computation time. Using serial-in-parallel-out multiplication, the design of the algorithm is highly regular, modular, and well suited for VLSI implementation
  • Keywords
    computational complexity; digital arithmetic; GF (2m); VLSI implementation; fast inversion; serial-in-parallel-out multiplication; Algorithm design and analysis; Computer architecture; Cryptography; Decoding; Error correction codes; Galois fields; Pipelines; Reed-Solomon codes; Signal processing algorithms; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computers, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9340
  • Type

    jour

  • DOI
    10.1109/12.35833
  • Filename
    35833
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1237048