• DocumentCode
    1237069
  • Title

    ABRM: Adaptive  \\beta -Ratio Modulation for Process-Tolerant Ultradynamic Voltage Scaling

  • Author

    Hwang, Myeong-Eun ; Roy, Kaushik

  • Author_Institution
    Intel, Hillsboro, OR, USA
  • Volume
    18
  • Issue
    2
  • fYear
    2010
  • Firstpage
    281
  • Lastpage
    290
  • Abstract
    Subthreshold operation of digital circuits has emerged as a promising approach to achieve ultralow power dissipation. However, extensive application of subthreshold logic is limited due to low performance and high susceptibility to process variation (PV). This paper proposes a PV-tolerant ultradynamic voltage scaling (UDVS) system where performance requirements dictate whether the devices will work in the subthreshold or superthreshold region. Due to different mechanisms of current conduction, it is necessary to use different P/N ratios for different regions of operation to improve circuit robustness, performance, and power. With an analytical model of circuit robustness, we present an adaptive body-biasing technique to dynamically adjust the ??-ratio depending on the operating region. Measurements show that our methodology improves the dynamic range of operation the circuits-from 1.2 V all the way down to 85 mV consuming 40 nW (at 85 mV) of power for an 8 × 8 finite-impulse response filter fabricated in a 0.13-??m technology, and can salvage circuits which otherwise would fail to operate due to device mismatches and skewed P/N ratios.
  • Keywords
    FIR filters; adaptive modulation; circuit simulation; logic circuits; ABRM; adaptive ??-ratio modulation; adaptive body-biasing technique; analytical model; circuit robustness; device mismatches; digital circuits; finite-impulse response filter; process variation; process-tolerant ultradynamic voltage scaling; size 0.13 mum; subthreshold logic; subthreshold operation; superthreshold region; ultralow power dissipation; voltage 1.2 V to 85 mV; P/N ratio; $ beta$ -ratio; Dynamic voltage scaling (DVS); low power; process variation (PV); subthreshold logic;
  • fLanguage
    English
  • Journal_Title
    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1063-8210
  • Type

    jour

  • DOI
    10.1109/TVLSI.2008.2010767
  • Filename
    4814475