Title :
Acquisition-time estimation for over 10 Gbit/s clock and data recovery ICs
Author :
Kishine, K. ; Onodera, H.
Author_Institution :
NTT Microsyst. Integration Labs., Atsugi, Japan
Abstract :
A method to estimate the acquisition time for the clock and data recovery (CDR) IC using the linear phase-locked loop (PLL) technique is proposed. Estimations using the method follow the measured acquisition time for the PLL with any loop parameters, which makes it possible to design the CDR IC for various targets.
Keywords :
bipolar digital integrated circuits; clocks; phase locked loops; synchronisation; timing circuits; 10 Gbit/s; acquisition-time estimation; clock and data recovery integrated circuit; linear phase locked loop;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20052776
