DocumentCode
1237546
Title
Architecturally efficient FFT pruning algorithm
Author
Singh, S. ; Srinivasan, S.
Author_Institution
Dept. of Electr. Eng., Indian Inst. of Technol. Madras, Chennai, India
Volume
41
Issue
23
fYear
2005
Firstpage
1305
Lastpage
1306
Abstract
Several fast Fourier transform (FFT) pruning algorithms have been proposed for applications where the entire spectrum of frequencies is not of relevance and even the inputs are sparse. However, these are architecturally inefficient because of the complexity of the overhead operations involved. Developed is a new generic pruning algorithm that uses only single bit combinational operations for delineating paths in the signal flow graph, as against butterflies, which are relevant for computation of the desired frequency coefficients. The entire delineation process has been divided into stages making the proposed algorithm also amenable for pipelined hardware implementation.
Keywords
combinatorial mathematics; digital arithmetic; fast Fourier transforms; signal flow graphs; FFT pruning algorithm; combinational operation; delineation process; fast Fourier transform; generic pruning algorithm; pipelined hardware implementation; signal flow graph;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20052994
Filename
1541788
Link To Document